Chemical mechanical polishing simulation methods and simulation devices thereof

ABSTRACT

A CMP simulation method includes inputting a chip pattern layout including a plurality of graphic patterns, partitioning the chip pattern layout into targeting grids including a plurality of surrounding grids, and then calculating grid geometry characteristics of the targeting grids. The CMP simulation method also includes generating shifted grids by shifting the targeting grids, calculating weighted average grid geometry characteristics of the targeting grids and of the shifted grids, and locating first hot spots on the chip pattern layout by performing a CMP simulation based on the grid geometry characteristics of the targeting grids. Further, the CMP simulation method includes generating optimized grid geometry characteristics by modifying the grid geometry characteristics of the targeting grids based on the weighted average grid geometry characteristics and the defined first hot spots, and then locating second hot spots on the chip pattern layout by performing the CMP simulation based on the optimized grid geometry characteristics.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims the priority of Chinese Patent Application No. CN201610221234.8, filed on Apr. 11, 2016, the entire content of which is incorporated herein by reference.

FIELD OF THE DISCLOSURE

The present disclosure generally relates to the field of polishing technology and, more particularly, relates to chemical mechanical polishing simulation methods and simulation devices thereof.

BACKGROUND

Chemical mechanical polishing (CMP) process is a mainstream planarization process in current semiconductor fabrication technology. Specifically, CMP process uses a method combining chemical grinding material with mechanical polishing to planarize the surface of wafer. In general, the mechanism of CMP process is as follows: a large amount of polishing fluid containing quartz sand particles is disposed on a polishing pad; materials on the surface of the wafer, especially on the protruding areas of the wafer, may react with the polishing fluid, and thus form a surface layer that can be easily removed; as the surface of the wafer moves relative to the polishing pad, the surface layer may be mechanically removed under the pressure applied by the polishing particles, and as a result, the surface of the wafer may be planarized.

Because the CMP process utilizes the interplay of chemical reaction and physical removal as well as other effects, the CMP process may be affected by many factors, such as the size of the polishing particles, the property of the polishing pad, the applied pressure, the relative speed between the polishing pad and the wafer, etc. Such factors may all have significant influence on the surface profile of the chip obtained after the CMP process. In some cases, when one or more of the above factors are not in the optimal condition, the planarization process may not reach desired results.

In order to reduce the production cost of a CMP process, a reasonable prediction on the surface profile of the chip to be obtained after the CMP process may be required. Specifically, hot spots that may appear on the chip surface may be pre-evaluated. Such hot spots may be the spots where the thickness of the pattern on the chip surface exceeds a predetermined thickness range, or where the difference between the height of the pattern on the chip surface and the height of a reference plane exceeds a predetermined height range, including microscopically raised and recessed spots on the chip surface. Hot spots may lead to a number of problems such as short circuits caused by material residue of the CMP process, graphic bridging due to the height difference on the surface of the silicon wafer exceeding the process window of the photolithography process, the resistance and capacitance values exceeding specifications during electrical testing of the wafer, etc. The surface profile of a wafer to be obtained after a CMP process is usually predicted by CMP simulation software.

According to existing technology, the flow to predict the surface profile of a wafer after a CMP process usually includes inputting a chip pattern layout, grid-partitioning the chip pattern layout, calculating the pattern characteristics of the grids, using the calculated grid geometry characteristics as parameters in the CMP simulation software to simulate the CMP process, and finally, outputting the hot spots.

However, using the existing method described above to predict the surface profile of a chip obtained after a CMP process may often lead to inaccurate predictions. The disclosed CMP simulation method and the simulation device are directed to solve one or more problems set forth above and other problems in the art.

BRIEF SUMMARY OF THE DISCLOSURE

One aspect of the present disclosure includes a chemical mechanical polishing (CMP) simulation method. The CMP simulation method includes inputting a chip pattern layout including a plurality of graphic patterns, partitioning the chip pattern layout into targeting grids including a plurality of surrounding grids, and then calculating grid geometry characteristics of the targeting grids. The CMP simulation method also includes generating shifted grids by shifting the targeting grids, calculating weighted average grid geometry characteristics of the targeting grids and of the shifted grids, and locating first hot spots on the chip pattern layout by performing a CMP simulation based on the grid geometry characteristics of the targeting grids. Further, the CMP simulation method includes generating optimized grid geometry characteristics by modifying the grid geometry characteristics of the targeting grids based on the weighted average grid geometry characteristics and the defined first hot spots, and then locating second hot spots on the chip pattern layout by performing the CMP simulation based on the optimized grid geometry characteristics.

Another aspect of the present disclosure provides a CMP simulation device. The CMP simulation device includes a chip pattern layout input module, a targeting grids data module, a hot spot location module, a grids shift data module, and a grid geometry characteristic optimization module. The chip pattern layout input module is configured to input a chip pattern layout including a plurality of graphic patterns. The targeting grids data module is configured to partition the chip pattern layout into targeting grids and also calculates grid geometry characteristics of the targeting grids. The hot spot location module is configured to perform a CMP simulation to locate first hot spots on the chip pattern layout based on the grid geometry characteristics of the targeting grids. The grids shift data module is configured to shift the targeting grids and generate shifted grids and also calculates weighted average grid geometry characteristics of the targeting grids and the shifted grids. The grid geometry characteristic optimization module is configured to generate optimized grid geometry characteristics by modifying the grid geometry characteristics of the targeting grids based on the weighted average grid geometry characteristics and the defined first hot spots. Moreover, the hot spot location module also performs the CMP simulation to locate second hot spots on the chip pattern layout based on the optimized grid geometry characteristics.

Other aspects of the present disclosure can be understood by those skilled in the art in light of the description, the claims, and the drawings of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

The following drawings are merely examples for illustrative purposes according to various disclosed embodiments and are not intended to limit the scope of the present disclosure.

FIG. 1 illustrates a flowchart of an exemplary CMP simulation process consistent with various disclosed embodiments of the present disclosure;

FIG. 2 illustrates a schematic view of exemplary targeting grids consistent with various disclosed embodiments of the present disclosure;

FIG. 3 illustrates a schematic view of graphic patterns in a surrounding grid of the targeting grids consistent with various disclosed embodiments of the present disclosure:

FIGS. 4-6 illustrate schematic diagrams for a method of generating various shifted grids adopted in an exemplary CMP simulation process consistent with various disclosed embodiments of the present disclosure;

FIGS. 7-8 illustrate schematic diagrams for an exemplary method of calculating weighted average grid geometry characteristics of the targeting grids and corresponding shifted grids in an exemplary CMP simulation process consistent with various disclosed embodiments of the present disclosure; and

FIG. 9 illustrates a schematic view of the function modules in an exemplary CMP simulation device consistent with various disclosed embodiments of the present disclosure.

DETAILED DESCRIPTION

Reference will now be made in detail to exemplary embodiments of the invention, which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

The present disclosure provides a CMP simulation method to improve the accuracy of hot spot prediction for CMP process. FIG. 1 shows a flowchart of an exemplary CMP simulation process consistent with disclosed embodiments.

Referring to FIG. 1, at the beginning of the simulation process, a chip pattern layout may be inputted (S11). The chip pattern layout may include a plurality of graphic patterns.

Further, the chip pattern layout may be partitioned into targeting grids including a plurality of surrounding grids, and the grid geometry characteristics of the targeting grids may then be calculated (S13). FIG. 2 shows a schematic view of exemplary targeting grids consistent with disclosed embodiments.

Referring to FIG. 2, the chip pattern layout may be partitioned into targeting grids 11 along a first direction x and a second direction y. The targeting grids 11 may include a plurality of surrounding grids 101. The plurality of surrounding grids in the targeting grids 11 may all have an identical shape and an identical size.

In one embodiment, the chip pattern layout may have a size of 1000 μm×1000 μm. The chip pattern layout may then be partitioned into 50×50 surrounding grids 101 along the first direction x and the second direction y. The 50×50 surrounding grids 101 may all have a same shape with identical dimensions. Therefore, each surrounding grid may have a square shape and may have a size of 20 μm×20 μm. The size of the surrounding grids 101 may be smaller than or equal to the planarization length of the chip pattern layout.

In other embodiments, the chip pattern layout may also be partitioned into targeting grids including a plurality of surrounding grids with different shapes and/or different sizes. For example, the surrounding grids may have a rectangular shape or a diamond shape.

Further, the grid geometry characteristics of the targeting grids may be calculated. The grid geometry characteristics of each surrounding grid may include parameters reflecting the occupied area, the distribution of the graphic patterns within the surrounding grid, the height of the graphic patterns relative to a reference plane, etc. For example, the grid geometry characteristics of a surrounding grid may include the pattern density, the linewidth of the graphic patterns, the perimeter of the graphic patterns, the height of the graphic patterns, etc.

In one embodiment, calculating the grid geometry characteristics of the targeting grids may include separately calculating the pattern density, the linewidth of the graphic patterns, and the perimeter of the graphic patterns for each surrounding grid.

In other embodiments, calculating the grid geometry characteristics of the targeting grids may include calculating the pattern density, the linewidth of the graphic patterns, the distance between the graphic patterns, etc. for each surrounding grid. In general, any geometric characteristics of the targeting grids that reflect the information of the graphic patterns and the surface height of the chip pattern layout may be calculated.

In one embodiment, the number of the surrounding grids along the first direction x in the targeting grids may be N and the number of the surrounding grids along the second direction y in the targeting grids may be M. That is, the targeting grids are formed as a matrix of surrounding grids with N columns arranged along the first direction x and M rows arranged along the second direction y. Moreover, surrounding grid (i, j) may then be used to denote a surrounding grid located at the i^(th) column and j^(th) row of the N×M matrix of the surrounding grids, where both i and j are positive integers with 1≦i≦N and 1≦j≦M. Further, the number of graphic patterns included in the surrounding grid (i, j) may be T. In one embodiment, the method to calculate the grid geometry characteristics of the targeting grids may include the following aspects.

First, the pattern density in a surrounding grid (i, j) may be calculated through d_(ij)=Σ_(t=1) ^(T)d_(t), d_(t)=S_(t)/(D_(i)×D_(j)), where S_(t) is the area size of the t^(th) graphic pattern in the surrounding grid (i, j), D_(i)×D_(j) is the area size of the surrounding grid (i, j), and d_(t) is of the contribution of t^(th) graphic pattern to the pattern density of the surrounding grid (i, j).

Second, the linewidth of the graphic patterns in a surrounding grid (i, j) may be calculated through w_(ij)Σ_(t=1) ^(T)w_(t)S_(t)/Σ_(t=1) ^(T)S_(t), where w_(t) is the linewidth of the t^(th) graphic pattern in the surrounding grid (i, j), and S_(t) is the area size of the t^(th) graphic pattern in the surrounding grid (i, j).

Third, the perimeter of the graphic patterns in a surrounding grid (i, j) may be calculated through p_(ij)=Σ_(t=1) ^(T)p_(t), where p_(t) is the perimeter of the t^(th) graphic pattern in the surrounding grid (i, j). Specifically, p_(t) is the total length of the edges of the t^(th) graphic pattern inside the surrounding grid (i, j); that is, the length of the edges of the t^(th) graphic pattern outside the surrounding grid (i, j) or the length of the edges of the t^(th) graphic pattern at the boundary of the surrounding grid (i, j) may not be included in p_(t).

Further, by successively changing the value of i from 1 to N and the value of j from 1 to M, the pattern density d_(ij), the linewidth of the graphic patterns w_(ij), and the perimeter of the graphic patterns p_(ij) of each surrounding grid (i, j) may be calculated, and thus the grid geometry characteristics of the targeting grids may be obtained.

In one embodiment, the t^(th) graphic pattern in the surrounding grid (i, j) may have a rectangular shape. Thus, according to the method described above, calculating the linewidth of the t^(th) graphic pattern, w_(t), is equivalent to calculating the width of the rectangle.

In other embodiments, the t^(th) graphic pattern in the surrounding grid (i, j) may have an irregular shape. Accordingly, the method to calculate the linewidth of the t^(th) graphic pattern, w_(t), include the following steps. First, the t^(th) graphic pattern may be divided into a number of sub graphic patterns with each sub graphic pattern having a rectangular shape. Then, the linewidth of each sub graphic pattern may be calculated through w_(t)=Σ_(q=1) ^(Q)w_(tq)S_(tq)/Σ_(q=1) ^(Q)S_(tq), where Q is the number of the sub graphic patterns the t^(th) graphic pattern divided into, w_(tq) is the linewidth of the q^(th) sub graphic pattern of the t^(th) graphic pattern, and S_(tq) is the area size of the q^(th) sub graphic pattern of the t^(th) graphic pattern.

FIG. 3 shows a schematic view of graphic patterns in a surrounding grid of the targeting grids. Referring to FIG. 3, in one embodiment, a chip pattern layout is partitioned into targeting grids 21, and the targeting grids 21 include N×M=900 (N=30 and M=30) surrounding grids. The method to calculate the grid geometry characteristics of the targeting grids 21 may include the following steps.

The pattern density d₁₁, the linewidth of the graphic patterns w₁₁, and the perimeter of the graphic patterns p₁₁ of the sub grid 201, e.g. the sub grid (1,1), in the targeting grids 21 may be calculated. The area size of the sub grid 201 is D₁×D₁. The sub grid 201 may include five graphic patterns: a first graphic pattern 2011, a second graphic pattern 2012, a third graphic pattern 2013, a fourth graphic pattern 2014, and a fifth graphic pattern 2015. All the five graphic patterns have a rectangular shape. Further, the information of each graphic pattern including perimeter, area size, and linewidth may then be extracted. Specifically, the extracted information may include the perimeter P₁, the area size S₁, and the linewidth W₁ of the first graphic pattern 2011, the perimeter P₂, the area size S₂, and the linewidth W₂ of the second graphic pattern 2012, the perimeter P₃, the area size S₃, and the linewidth W₃ of the third graphic pattern 2013, the perimeter P₄, the area size S₄, and the linewidth W₄ of the fourth graphic pattern 2014, and the perimeter P₅, the area size S₅, and the linewidth W₅ of the fifth graphic pattern 2015. Because of the rectangular shape, the linewidth of each graphic pattern may be the width of the rectangle.

Moreover, the pattern density of the surrounding grid 201 may be calculated using d₁₁=Σ_(t=1) ⁵d_(t), d_(t)=S_(t)/(D₁×D₁), the linewidth of the graphic patterns may be calculated using w₁₁=Σ_(t=1) ⁵w_(t)S_(t)/Σ_(t=1) ⁵S_(t), and the perimeter of the graphic patterns may be calculated using p₁₁=Σ_(t=1) ⁵p_(t).

The method to calculate the grid geometry characteristics of the targeting grids 21 may further include calculating the pattern density d₁₂, the linewidth of the graphic patterns w₁₂, and the perimeter of the graphic patterns p₁₂ for the surrounding grids (1, 2), the pattern density d₁₃, the linewidth of the graphic patterns w₁₃, and the perimeter of the graphic patterns p₁₃ for the surrounding grid (1, 3), and so on, until the pattern density d₃₀₃₀, the linewidth of the graphic patterns w₃₀₃₀, and the perimeter of the graphic patterns p₃₀₃₀ of the surrounding grid (30, 30) are obtained. As such, the pattern density, the linewidth of the graphic patterns, the perimeter of the graphic patterns for all the surrounding grids in the targeting grids 21 are calculated to obtain the grid geometry characteristics of the targeting grids 21.

In one embodiment, to obtain the grid geometry characteristics of the targeting grids, the calculations for the surrounding grids (i, j) may not be limited to any specific order. Any calculation process that can provide the pattern density d_(ij), the linewidth of the graphic patterns w_(ij), and the perimeter of the graphic patterns p_(ij) for all the surrounding grids (i, j) in the targeting grids 21 may be adopted.

Further, returning to FIG. 1, the targeting grids may be shifted to obtain shifted grids, and weighted average grid geometry characteristics of the targeting grids and the shifted grids may be obtained through calculation (S15).

In one embodiment, a chip pattern layout may be partitioned into targeting grids along a first direction and a second direction. The targeting grids may include a plurality of surrounding grids with an identical shape and an identical size. The dimension of each surrounding grid along the first direction may be D_(i) and the dimension of each surrounding grid along the second direction may be D_(j). The targeting grids may then be shifted to obtain shifted grids. The shifted grids may be generated from the targeting grids by the following methods: first, the targeting grids may be shifted a distance of D_(i)/n along the first direction to obtain first shifted grids; second, the targeting grids may be shifted a distance of D_(j)/n along the second direction to obtain second shifted grids; and third, the targeting grids may be shifted a distance of D_(i)/n along the first direction and then shifted a distance of D_(j)/n along the second direction to obtain third shifted grids, where n is a positive integer.

Further, the method to calculate the weighted average grid geometry characteristics of the targeting grids and the shifted grids may include the following steps: calculating the grid geometry characteristics for the first shifted grids, the second shifted grids, and the third shifted grids, respectively, then using a weighted average method to calculate the weighted average grid geometry characteristics of the targeting grids, the first shifted grids, the second shifted grids, and the third shifted grids.

FIGS. 4-6 show schematic diagrams for a method adopted in an exemplary CMP simulation process to generate different shifted grids. Referring to FIGS. 4-6, in one embodiment, targeting grids 30 may include a plurality of surrounding grids with an identical shape and an identical dimension. The dimensions of a surrounding grid 301 along a first direction x and along a second direction y may be both equal to D_(i). Further, to generate shifted surrounding grids, the surrounding grid 301 may be shifted a distance of D_(i)/n along a first direction and/or along a second direction. In one embodiment, the number n may be 2. Accordingly, the targeting grids 30 may be shifted to obtain various shifted grids. The method to generate shifted grids may include shifting the targeting grids 30 a distance of D_(i)/2 along the first direction x to obtain first shifted grids 31 (indicated by dashed lines in FIG. 4), shifting the targeting grids 30 a distance of D_(i)/2 along the second direction y to obtain second shifted grids 32 (indicated by dashed lines in FIG. 5), and shifting the targeting grids 30 a distance of D_(i)/2 along the first direction x and then a distance of D_(i)/2 along the second direction y to obtain third shifted grids 33 (indicated by dashed lines in FIG. 6).

Further, the method to calculate the weighted average grid geometry characteristics of the targeting grids 30 and the shifted grids may include calculating the grid geometry characteristics of the first shifted grids 31, the grid geometry characteristics of the second shifted grids 32, and the grid geometry characteristics of the third shifted grids 33, respectively, and then using a weighted average method to calculate the weighted average grid geometry characteristics of the targeting grids 30, the first shifted grids 31, the second shifted grids 32, and the third shifted grids 33.

For example, calculating the grid geometry characteristics of the first shifted grids 31, the grid geometry characteristics of the second shifted grids 32, and the grid geometry characteristics of the third shifted grids 33 may include separately calculating the pattern density d_(1ij), the linewidth of graphic patterns w_(1ij), and the perimeter of graphic patterns p_(1ij) for each surrounding grid (i, j) of the first shifted grids 31, the pattern density d_(2ij), the linewidth of graphic patterns w_(2ij), and the perimeter of graphic patterns p_(2ij) for each surrounding grid (i, j) of the second shifted grids 32, and the pattern density d_(3ij), the linewidth of graphic patterns w_(3ij), and the perimeter of graphic patterns p_(3ij) for each surrounding grid (i, j) of the third shifted grids 33, where the value of i is successively changed from 1 to N, while the value of j is successively changed from 1 to M. N is the number of the surrounding grids in the targeting grids 30 along the first direction x, while M is the number of the surrounding grids in the targeting grids 30 along the second direction.

The method to calculate the pattern density d_(1ij), d_(2ij), and d_(3ij), the linewidth of graphic patterns w_(1ij), w_(2ij), and w_(3ij), and the perimeter of graphic patterns p_(1ij), p_(2ij), and p_(3ij) for the first shifted grids 31, the second shifted grids 32, and the third shifted grids 33 may be similar to the method adapted to calculate the pattern density d_(0ij), the linewidth of graphic patterns w_(0ij), and the perimeter of graphic patterns p_(0ij) for the targeting grids 30 described above.

The weighted average grid geometry characteristics of the targeting grids 30 and the shifted grids may be obtained by using a weighted average method to average the grid geometry characteristics of the targeting grids 30, the first shifted grids 31, the second shifted grids 32, and the third shifted grids 33. The calculation of the weighted average grid geometry characteristics may include calculating the weighted average pattern density d_(ij) , the weighted average linewidth of graphic patterns w_(ij) , and the weighted average perimeter of graphic patterns p_(ij) for each surrounding grid (i, j).

FIGS. 7-8 show schematic diagrams for an exemplary method used to calculate the weighted average grid geometry characteristics of a surrounding grid of the targeting grids and the corresponding shifted grids in an exemplary CMP simulation process.

Referring to FIGS. 7-8, nine surrounding grids are shown in the two figures. Specifically, a surrounding grid (i, j) of the targeting grids 30 is denoted as 301 in each figure; a surrounding grid (i, j) and a surrounding grid (i+1, j) of the first shifted grids 31 are denoted as 311 and 312, respectively; a surrounding grid (i, j) and a surrounding grid (i, j+1) of the second shifted grids 32 are denoted as 321 and 322, respectively; and surrounding grids (i, j), a surrounding grid (i+1, j), a surrounding grid (i, j+1), and a surrounding grid (i+l, j+1) of the third shifted grids 33 are denoted as 331, 332, 333, and 334, respectively.

Further, the weighted average pattern density of the surrounding grids (i, j) is given by d_(ij) (e₀d_(0ij)+e₁d_(1ij)+e₁d_(1(i+1)j)+e₂d_(2ij)+e₂d_(2i(j+1))+e₃d_(3ij)+e₃d_(3(i+1)j)+e₃d_(3i(j+1))+e₃d_(3(i+1)(j+1))/(e₀+2e₁+2e₂+4e₃), where d_(0ij) is the pattern density of the surrounding grid 301: d_(1ij) and d_(1(i+1)j) are the pattern densities of the surrounding grids 311 and the surrounding grids 312, respectively; d_(2ij) and d_(2i(j+1)), are the pattern densities of the surrounding grid 321 and the surrounding grid 322, respectively; d_(3ij), d_(3(i+1)j), d_(3i(j+1)), and d_(3(i+1)(j+1)) are the pattern densities of the surrounding grid 331, the surrounding grid 332, the surrounding grid 333, and the surrounding grid 334, respectively: and e₀, e₁, e₂, and e₃ are first weight factors used to weight the surrounding grid 301 of the targeting grids 30, the surrounding grids 311 and 312 of the first shifted grids 31, the surrounding grids 321 and 322 of the second shifted grids 32, and the surrounding grids 331, 332, 333, and 334 of the third shifted grids 33, respectively in the formula to calculate the weighted average pattern density d_(ij) .

The weighted average linewidth of graphic patterns of the surrounding grid (i, j) is given by w_(i) =f₀w_(0ij)+f₁w_(1ij)+f₁w_(1(i+1)j)+f₂w_(2ij)+f₂w_(2i(j+1))+f₃w_(3ij)+f₃w_(3(i+1)j)+f₃w_(3i(j+1))+f₃w_(3(i+1)(j+1))/(f₀+2f₁+2f₂+4f₃), where w_(0ij) is the linewidth of graphic patterns of the surrounding grid 301: w_(1ij) and w_(1(i+1)j) are the linewidths of graphic patterns of the surrounding grid 311 and the surrounding grid 312, respectively; w_(2ij) and w_(2i(j+1)) are the linewidths of graphic patterns of the surrounding grid 321 and the surrounding grid 322, respectively; w_(3ij), w_(3(i+1)j), w_(3i(j+1)), and w_(3(i+1)(j+1)) are the linewidths of graphic patterns of the surrounding grid 331, the surrounding grid 332, the surrounding grid 333, and the surrounding grid 334, respectively; and f₀, f₁, f₂, and f₃ are second weight factors used to weight the surrounding grid 301 of the targeting grids 30, the surrounding grids 311 and 312 of the first shifted grids 31, the surrounding grids 321 and 322 of the second shifted grids 32, and the surrounding grids 331, 332, 333, and 334 of the third shifted grids 33, respectively in the formula to calculate the weighted average linewidth of graphic patterns w_(ij) .

The weighted average perimeter of graphic patterns of the surrounding grid (i, j) is given by p_(i) =g₀p_(0ij)+g₁p_(1ij)+g₁p_(1(i+1)j)+g₂p_(2ij)+g₂p_(2i(j+1))+g₃p_(3ij)+g₃p_(3(i+1)j)+g₃p_(3i(j+1))+g₃p_(3(i+1)(j+1))/(g₀+2g₁+2g₂+4g₃), where p_(0ij) is the perimeter of graphic patterns of the surrounding grid 301: p_(1ij) and p_(1(i+1)j) are the perimeters of graphic patterns of the surrounding grid 311 and the surrounding grid 312, respectively; p_(2ij) and p_(2i(j+1)) are the perimeters of graphic patterns of the surrounding grid 321 and the surrounding grid 322, respectively; p_(3ij), p_(3(i+1)j), p_(3i(j+1)), and p_(3(i+1)(j+1)) are the perimeters of graphic patterns of the surrounding grid 331, the surrounding grid 332, the surrounding grid 333, and the surrounding grid 334, respectively; and g₀, g₁, g₂, and g₃ are second weight factors used to weight the surrounding grid 301 of the targeting grids 30, the surrounding grids 311 and 312 of the first shifted grids 31, the surrounding grids 321 and 322 of the second shifted grids 32, and the surrounding grids 331, 332, 333, and 334 of the third shifted grids 33, respectively in the formula to calculate the weighted average perimeter of graphic patterns p_(ij) .

According to the weighted average method, weight factors may be used to calculate the weighted average grid geometry characteristics such as the weighted average pattern density, the weighted average linewidth of graphic patterns, the weighted average perimeter of graphic patterns, etc. Further, in a subsequent process, the weighted average grid geometry characteristics may be used to modify the grid geometry characteristics of targeting grids and generate optimized grid geometry characteristics. As such, the optimized grid geometry characteristics may have the effect of surrounding grids taken into account.

In some cases, the first weight factors, the second weight factors, and the third weight factors may be obtained by a least square fitting method. In some of other cases, the first weight factors, the second weight factors, and the third weight factors may also be assigned with empirical values and the empirical values may then be modified based on CMP simulation results.

In one embodiment, the first weight factors may be e₀=1, e₁=0.5, e₂=0.5, and e₃=0.25; the second weight factors may be f₀=1, f₁=0.5, f₂=0.5, and f₃=0.25; and the third weight factors may be g₀=1, g₁=0.5, g₂=0.5, and g₃=0.25.

Moreover, when the targeting grids 30 are shifted to provide the first shifted grids 31, the second shifted grids 32, and the third shifted grids 33, the number of the surrounding grids in the shifted grids may remain unchanged. That is, the first shifted grids 31, the second shifted grids 32, and the third shifted grids 33 may all be N×M matrices of surrounding grids. Further, using the method described above to calculate the weighted average grid geometry characteristics of surrounding grids (N, j) or surrounding grids (i, M), the first shifted grids 31 may not be able to provide grid geometry characteristics for surrounding grids (N+1, j), the second shifted grids 32 may not be able to provide grid geometry characteristics for surrounding grid (i, M+1), and the third shifted grids 33 may not be able to provide grid geometry characteristics for surrounding grid (i, M+1), surrounding grid (N+1, j), and surrounding grid (N+1, M+1), where 1≦i≦N and 1≦j≦M.

In order to avoid the problem described above, in one embodiment, the first shifted grids 31 may have a series of extra surrounding grids (N+1, j), where 1≦j≦M. That is, the number of the surrounding grids included in the first shifted grids 31 may be (N+1)×M. Similarly, the second shifted grids 32 may have a series of extra surrounding grids (i, M+1), where 1≦i≦N. That is, the number of the surrounding grids included in the second shifted grids 32 may be N×(M+1). Moreover, the third shifted grids 33 may have an extra row of surrounding grids (i, M+1) and an extra column of surrounding grids (N+1, j), where 1≦i≦N and 1≦j≦M. That is, the number of the surrounding grids included in the third shifted grids 33 may be (N+1)×(M+1).

According to the method described above, the obtained weighted average grid geometry characteristics of the surrounding grid (i, j) are in fact the weighted average results of the surrounding grid (i, j) of the targeting grids 30 and the eight surrounding grids of the three shifted grids that are partially overlapping with the surrounding grid (i, j) of the targeting grids 30. The eight surrounding grids may include surrounding grids (i, j) and (i+1, j) of the first shifted grids 31, surrounding grids (i, j) and (I, J+1) of the second shifted grids 32, and surrounding grids (i, j), (i+1, j), (i, j+1), and (i+1, j+1) of the third shifted grids 33. Therefore, the weighted average grid geometry characteristics may reflect the long-range correlation effect between neighboring surrounding grids. Specifically, compared to the grid geometry characteristics of the targeting grids, the weighted average grid geometry characteristics may capture all grid geometry characteristics of the chip surface more precisely, and thus may avoid extracting inaccurate grid geometry characteristics for graphic patterns at the boundaries of surrounding grids due to grid partitioning.

Further, returning to FIG. 1, based on the extracted grid geometry characteristics of the targeting grids, CMP simulation may then be performed to locate first hot spots on the chip pattern layout (S17).

Specifically, a CMP simulation model may be selected. The pattern density d_(ij), the linewidth of graphic patterns w_(ij), and the perimeter of graphic patterns p_(ij) of each surrounding grid in the targeting grids may be inputted as parameters for the CMP simulation model. Then, CMP simulation may be performed to locate the position of the first hot spots on the chip pattern layout. The CMP simulation model may be a process-based mathematical physics model that may be able to reflect corresponding process parameters and may simulate the process results of the designed layout.

In one embodiment, the chip may include a plurality of graphic patterns as well as a dielectric layer. In addition, a base plane may be defined as a plane with a height equal to an average height of the top surface of the graphic patterns and the top surface of the dielectric layer. After the CMP simulation process, a portion of the graphic patterns on the chip surface may have a height difference relative to the base plane exceeding 200 Å, and thus the corresponding spots on the chip surface may then be defined as the first hot spots.

In other embodiments, the chip may include a plurality of graphic patterns as well as a dielectric layer. After the CMP simulation process, the thickness of a portion of the graphic patterns on the chip surface may exceed 110% of a standard graphic pattern thickness, and thus the corresponding spots on the chip surface may then be defined as the first hot spots. Specifically, the standard graphic pattern thickness may be a preset thickness and the preset thickness may be determined according to process feature and experience by different technology nodes.

In one embodiment, the graphic patterns on the chip may be copper wires, the dielectric layer may be SiO_(x), and after the CMP simulation process, a standard thickness of the copper wires may be 1500 Å. Accordingly, spots on the chip surface corresponding to copper wires with a thickness larger than 1650 (e.g. 1500+150) Å or smaller than 1350 (e.g. 1500-150) Å may be defined as first hot spots.

The first hot spots may not be limited to several specific definitions. In fact, different methods may be used to define the first hot spots. The first hot spots may be defined by methods based on actual requirements of the CMP process. The first hot spots may be defined by one or a combination of multiple definition methods.

Returning to FIG. 1, further, optimized grid geometry characteristics may be obtained by revising the grid geometry characteristics of the targeting grids based on the weighted average grid geometry characteristics of the targeting grids and the shifted grids, and also based on the defined first hot spots (S19). The method to obtain the optimized grid geometry characteristics may include using the weighted average grid geometry characteristics to replace the grid geometry characteristics of the surrounding grids that correspond to the defined first hot spots in the targeting grids; while the grid geometry characteristics of the surrounding grids in the targeting grids not corresponding to the first hot spots may remain unchanged.

In one embodiment, the first hot spots may be surrounding grids (g, h) of the targeting grids, where 1≦i≦N and 1≦j≦M, while both i and j are positive integers. Accordingly, the grid geometry characteristics of the surrounding grids (g, h) of the targeting grids, including the pattern density d_(gh), the linewidth of graphic patterns w_(gh), and the perimeter of graphic patterns p_(gh) may be replaced by the weighted average grid geometry characteristics of the surrounding grids (g, h), including the weighted average pattern density d_(gh) , the weighted average linewidth of graphic patterns w_(gh) , and the weighted average perimeter of graphic patterns p_(gh) . In addition, except for the surrounding grids defined as the first spots, the grid geometry characteristics for other surrounding grids (n, m) of the targeting grids, such as d_(nm), w_(nm), and p_(nm) (1≦n≦N and 1≦m≦M; both n and m are positive integers; when n=g, then m≠h; and when m=h, n≠g), may remain unchanged. As such, the weighted average grid geometry characteristics d_(gh) , w_(gh) , and p_(gh) of the surrounding grids (g, h), i.e. the first hot spots, and the grid geometry characteristics d_(nm), w_(nm), and p_(nm) of the other surrounding grids (n, m) in the targeting grids may together form the optimized grid geometry characteristics.

Further, returning to FIG. 1, based on the optimized grid geometry characteristics, CMP simulation may be performed to locate second hot spots on the chip pattern layout (S21).

Specifically, the method to locate the second hot spots may include the following steps. First, a CMP simulation model may be selected. The optimized grid geometry characteristics may be inputted as parameters for the CMP simulation model. Then, CMP simulation may be performed to locate the position of the second hot spots on the chip pattern layout. In one embodiment, the CMP simulation model may be a process-based mathematical physics model and the method to locate the second hot spots may be similar to the method to locate the first hot spots.

In one embodiment, the chip may include a plurality of graphic patterns as well as a dielectric layer. In addition, a base plane may be defined as a plane with a height equal to an average height of the top surface of the graphic patterns and the top surface of the dielectric layer. After the CMP simulation process, a portion of the graphic patterns on the chip surface may have a height difference relative to the base plane exceeding 200 Å, and thus the corresponding spots on the chip surface may then be defined as the second hot spots.

In other embodiments, the chip may include a plurality of graphic patterns as well as a dielectric layer. After the CMP simulation process, the thickness of a portion of the graphic patterns on the chip surface may exceed 110% of a standard graphic pattern thickness, and thus the corresponding spots on the chip surface may then be defined as the second hot spots. Specifically, the standard graphic pattern thickness may be a preset thickness and the preset thickness may be determined according to experience.

In one embodiment, the graphic patterns on the chip may be copper wires, the dielectric layer may be SiO_(x), and after the CMP simulation process, a standard thickness of the copper wires may be 1500 Å. Accordingly, spots on the chip surface corresponding to copper wires with a thickness larger than 1650 (e.g. 1500+150) Å or smaller than 1350 (e.g. 1500-150) Å may be defined as second hot spots.

The second hot spots may not be limited to several specific definitions. In fact, different methods may be used to define the second hot spots. The second hot spots may be defined by methods based on actual requirements of the CMP process. The second hot spots may be defined by one or a combination of multiple definition methods.

According to the disclosed CMP simulation method, the weighted average grid geometry characteristics of the targeting grids and the shifted grids may be used to revise the grid geometry characteristics of the surrounding grids at the first hot spots of the targeting grids. Further, CMP simulation may be performed to locate the second hot spots existing on the chip pattern layout. Because the weighted average grid geometry characteristics may take the long-range correlation effect between neighboring surrounding grids in the targeting grids into account, the weighted average grid geometry characteristics may reflect the grid geometry characteristics of the surrounding grids at the defined first hot spots more accurately. Therefore, the possibility of having false prediction on the location of the second hot spots may be reduced, and thus the accuracy of the CMP simulation may be improved.

According to the disclosed CMP simulation method, after locating the first hot spots, only the grid geometry characteristics of the surrounding grids in the targeting grids corresponding to the first hot spots may be modified. The reasons to avoid using the average grid pattern characteristics to replace the grid geometry characteristics for all surrounding grids in the targeting grids lie in two aspects: first, revising the grid geometry characteristics of the surrounding grids only corresponding to the first hot spots may avoid introducing a series of problems, such as prediction error for individual points on the silicon wafer, change in the mean value of the prediction results for the entire silicon wafer, etc.; second, the partial modification for the grid geometry characteristics may also avoid introducing new hot spots and thus affecting the accuracy of the CMP simulation results.

The present disclosure also provides a simulation device for CMP simulation. FIG. 9 shows a schematic view of the function modules in an exemplary CMP simulation process consistent with disclosed embodiments.

Referring to FIG. 9, the simulation device may include a chip pattern layout input module 400, a targeting grids data module 401, a hot spots location module 402, a grids shift data module 403, and a grid geometry characteristic optimization module 404.

Specifically, the chip pattern layout input module 400 may be used to input chip pattern layout which may include a plurality of graphic patterns. The targeting grids data module 401 may be used to partition the chip pattern layout into targeting grids. The targeting grids may include a plurality of surrounding grids. The targeting grids data module 401 may also calculate the grid geometry characteristics of the targeting grids. The hot spots location module 402 may be used to perform CMP simulation based on the grid geometry characteristics of the targeting grids. The CMP simulation may result in locating first hot spots existing on the chip pattern layout. The grids shift data module 403 may be used to create shifted grids by shifting the targeting grids. The grids shift data module 403 may also calculate the weighted average grid geometry characteristics of the targeting grids and the shifted grids. The grid geometry characteristic optimization module 404 may be used to revise the grid geometry characteristics of the targeting grids based on the weighted average grid geometry characteristics and the located first hot spots, and thus generate optimized grid geometry characteristics. Moreover, the hot spots location module 402 may also be used to perform CMP simulation to locate second hot spots based on the optimized grid geometry characteristics.

In one embodiment, the chip may include a plurality of graphic patterns as well as a dielectric layer. The definition of the first hot spots and the definition of the second hot spots may be the same: the portion of the chip surface with the top graphic patterns having a height difference relative to a base plane exceeding 200 Å after the CMP simulation process. Specifically, the base plane may be defined as a plane with a height equal to an average height of the top surface of the graphic patterns and the top surface of the dielectric layer.

In other embodiments, after the CMP simulation process, the first hot spots and/or the second hot spots may be defined as the portion of the chip surface with the top graphic patterns having a thickness exceeding 110% of a standard graphic pattern thickness. Specifically, the standard graphic pattern thickness may be a preset thickness and the preset thickness may be determined according to experience.

The first hot spots and/or the second hot spots may also be defined based on any other appropriate standards. Based on the actual requirements of the CMP process, the definition of the first hot spots and the definition of the second hot spots may or may not be the same.

In one embodiment, the grid geometry characteristics of the targeting grids may include three grid geometry characteristics: pattern density, linewidth of the graphic patterns, and perimeter of the graphic patterns. In other embodiments, the grid geometry characteristics of the targeting grids may include pattern density, linewidth of the graphic patterns, and distance between the graphic patterns, etc. In general, the grid geometry characteristics of the targeting grids may include any grid geometry characteristics that reflect the information of the graphic patterns on the chip pattern layout.

In one embodiment, the grids shift data module 403 may shift the targeting grids to obtain shifted grids, and then calculate the grid geometry characteristics for the shifted grids before using a weighted average method to calculate the weighted average grid geometry characteristics of the targeting grids and the shifted grids.

In one embodiment, the grid geometry characteristic optimization module 404 may revise the grid geometry characteristics of the targeting grids and thus generate optimized grid geometry characteristics. The method to obtain optimized grid geometry characteristics may include using the weighted average grid geometry characteristics to replace the grid geometry characteristics of surrounding grids that correspond to the defined first hot spots in the targeting grids; while the grid geometry characteristics of the surrounding grids in the targeting grids not corresponding to the first hot spots may remain unchanged. Thus, the weighted average grid geometry characteristics of the surrounding grids corresponding to the first hot spots together with the grid geometry characteristics of other surrounding grids (i.e. surrounding grids not corresponding to the first hot spots) may form the optimized grid geometry characteristics.

In one embodiment, the CMP simulation device may also include a grid geometry characteristic output module 405. The grid geometry characteristic output module 405 may be used to send the optimized grid geometry characteristics generated by the grid geometry characteristic optimization module 404 to the hot spots location module 402. The hot spots location module 402 may then perform CMP simulation to locate the second hot spots based on the inputted optimized grid geometry characteristics.

Compared to existing CMP simulation methods and existing CMP simulation devices, the disclosed CMP simulation method and simulation device may demonstrate several advantages.

According to the disclosed CMP simulation method, the chip pattern layout may be partitioned into targeting grids, and the grid geometry characteristics of the targeting grids may be calculated. Then, first hot spots may be obtained by performing CMP simulation using the grid geometry characteristics. The targeting grids may be shifted to obtain shifted grids and the weighted average grid geometry characteristics may then be calculated. Further, optimized grid geometry characteristics may be generated by using the weighted average grid geometry characteristics of the surrounding grids in the targeting grids to replace the grid geometry characteristics of the surrounding grids that correspond to the first hot spots. Finally, second hot spots may then be obtained by performing CMP simulation using the optimized grid geometry characteristics.

Because the weighted average grid geometry characteristics may take the long-range correlation effect between neighboring surrounding grids in the targeting grids into account, the weighted average grid geometry characteristics may reflect the grid geometry characteristics of the surrounding grids at the defined first hot spots more accurately. Therefore, the possibility of having false prediction on the location of the second hot spots may be reduced, and thus the accuracy of the CMP simulation may be improved.

Further, according to the disclosed CMP simulation methods, after locating the first hot spots, only the grid geometry characteristics of the surrounding grids in the targeting grids corresponding to the first hot spots may be modified. The reasons to avoid using the weighted average grid geometry characteristics to replace the grid geometry characteristics for all surrounding grids in the targeting grids lie in two aspects: first, revising the grid geometry characteristics of the surrounding grids corresponding only to the first hot spots may avoid introducing a series problems, such as prediction error for individual points on the silicon wafer, change in the mean value of the prediction results for the entire silicon wafer, etc.; second, the partial modification for the grid geometry characteristics may also avoid introducing new hot spots and thus affecting the accuracy of the CMP simulation results.

According to the disclosed CMP simulation device, the targeting grids data module may partition the chip pattern layout in to targeting grids and may then calculate the grid geometry characteristics for the targeting grids; the grids shift data module may generate weighted average grid geometry characteristics of the targeting grids and the shifted grids; the hot spot location module may perform CMP simulation to obtain first hot spots based on the grid geometry characteristics of the targeting grids; the grid geometry characteristic optimization module may generate optimized grid geometry characteristics by revising the grid geometry characteristics of the targeting grids based on the weighted average grid geometry characteristics and the defined first hot spots; and finally, the hot spot location module may perform CMP simulation to obtain second hot spots based on the optimized grid geometry characteristics.

Because the weighted average grid geometry characteristics may take the long-range correlation effect between neighboring surrounding grids in the targeting grids into account, the weighted average grid geometry characteristics may reflect the grid geometry characteristics of the surrounding grids at the defined first hot spots more accurately. Therefore, the possibility of having false prediction on the location of the second hot spots may be reduced, and thus the accuracy of the CMP simulation may be improved

Further, the modules and the methods described above may be realized through electronic hardware, computer software, or a combination of the two. In order to express the interchangeability between hardware and software, the above modules and the methods are generally described based on their functions. Depending on specific application and design constrains, the functions may be realized by hardware, software, or a combination of the two.

Moreover, the modules and the methods described above may be performed directly by hardware, a software module for processor execution, or a combination of the two. The software module may be stored in a random-access memory (RAM), an internal memory, read-only memory (ROM), an electrically programmable ROM, an electrically erasable ROM, a register memory, a hard disk, a removable disk, a compact disc read-only memory (CD-ROM), or any other appropriate storage media.

Moreover, the disclosed CMP simulation device and CMP simulation methods may be used to predict the positions of hot spots on a wafer prior to performing a CMP process. According to the disclosed CMP simulation device and CMP simulation methods, the chip pattern layout may be partitioned into targeting grids, and the grid geometry characteristics of the targeting grids may be calculated. Then, first hot spots may be located through CMP simulation based on the grid geometry characteristics. Moreover, shifted grids may be generated from the targeting grids and weighted average grid geometry characteristics of targeting grids and the corresponding shifted grids may be calculated. Further, by replacing the grid geometry characteristics of the surrounding grids that correspond to the first hot spots with the weighted average grid geometry characteristics, optimized grid geometry characteristics may be obtained. Finally, second hot spots may be obtained through CMP simulation using the optimized grid geometry characteristics.

Because the weighted average grid geometry characteristics may take the long-range correlation effect between neighboring surrounding grids in the targeting grids into account, the weighted average grid geometry characteristics may reflect the grid geometry characteristics of the surrounding grids at the defined first hot spots more accurately. Therefore, as compared to existing simulation devices and simulation methods, the disclosed simulation device and simulation methods may effectively filter the false CMP hot spots and may also avoid introducing new false hot spots during the process to locate the second hot spots.

Moreover, because the positions of hot spots of a wafer after a CMP process may be accurately predicted, the role of CMP process parameters may be examined using the disclosed CMP simulation device and simulation methods. Therefore, the simulation results may help improving the selection of CMP process parameters.

In addition, with the positions of hot spots precisely determined, the simulation results may also help improving the chip pattern layout design so that problems caused by CMP, such as short circuits, graphic bridging, overly large resistance and/or capacitance, etc., may be reduced.

The above detailed descriptions only illustrate certain exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention. Those skilled in the art can understand the specification as whole and technical features in the various embodiments can be combined into other embodiments understandable to those persons of ordinary skill in the art. Any equivalent or modification thereof, without departing from the spirit and principle of the present invention, falls within the true scope of the present invention. 

What is claimed is:
 1. A chemical mechanical polishing (CMP) simulation method, comprising: inputting a chip pattern layout including a plurality of graphic patterns; partitioning the chip pattern layout into targeting grids and calculating grid geometry characteristics of the targeting grids, wherein the targeting grids include a plurality of surrounding grids; generating shifted grids by shifting the targeting grids and calculating weighted average grid geometry characteristics of the targeting grids and of the shifted grids; locating first hot spots on the chip pattern layout by performing a CMP simulation based on the grid geometry characteristics of the targeting grids; generating optimized grid geometry characteristics by modifying the grid geometry characteristics of the targeting grids based on the weighted average grid geometry characteristics and the defined first hot spots; and locating second hot spots on the chip pattern layout by performing the CMP simulation based on the optimized grid geometry characteristics.
 2. The CMP simulation method according to claim 1, wherein: the chip pattern layout includes a dielectric layer in addition to the plurality of graphic patterns; and the first hot spots and the second hot spots are defined as a portion of the chip pattern layout with top graphic patterns having a height difference relative to a base plane exceeding 200 Å after a corresponding CMP simulation process, wherein: the dielectric layer isolates neighboring graphic patterns; and the base plane is defined as a plane with a height equal to an average height of top surfaces of the graphic patterns and a top surface of the dielectric layer.
 3. The CMP simulation method according to claim 1, wherein: the chip pattern layout includes a dielectric layer in addition to the plurality of graphic patterns; and the first hot spots and the second hot spots are defined as a portion of the chip pattern layout with the top graphic patterns having a thickness exceeding 110% of a standard graphic pattern thickness, wherein: the dielectric layer isolates neighboring graphic patterns; and the standard graphic pattern thickness is a preset thickness determined according to experience.
 4. The CMP simulation method according to claim 1, wherein: the chip pattern layout is partitioned into the targeting grids along a first direction and a second direction, wherein the plurality of surrounding grids of the targeting grids all have an identical shape and an identical size, a dimension of each surrounding grid along the first direction is D_(i), and a dimension of each surrounding grid along the second direction is D_(j); and shifting the targeting grids to generate the shifted grids includes shifting the targeting grids a distance of D_(i)/n along the first direction to form first shifted grids, shifting the targeting grids a distance of D_(j)/n along the second direction to form second shifted grids, and shifting the targeting grids a distance of D_(i)/n along the first direction and then a distance of D_(j)/n along the second direction to form third shifted grids, wherein n is a positive integer.
 5. The CMP simulation method according to claim 4, wherein calculating the weighted average grid geometry characteristics of the targeting grids and the shifted grids includes: separately calculating grid geometry characteristics for the first shifted grids, the second shifted grids, and the third shifted grids; and calculating the grid geometry characteristics of the targeting grids, the first shifted grids, the second shifted grids, and the third shifted grids using a weighted average method.
 6. The CMP simulation method according to claim 1, wherein: calculating the grid geometry characteristics of the targeting grids includes separately calculating pattern density, linewidth of graphic patterns, perimeter of graphic patterns for each surrounding grid of the targeting grids.
 7. The CMP simulation method according to claim 6, wherein: the chip pattern layout is partitioned into the targeting grids along a first direction and a second direction, wherein the plurality of surrounding grids in the targeting grids form a matrix having N surrounding grids along the first direction and M surrounding grids along the second direction; a surrounding grids located at the i^(th) column along the first direction and the jth row along the second direction is denoted as surrounding grids (i, j), where both i and j are positive integers with 1≦i≦N and 1≦j≦M; a number of graphic patterns in the surrounding grids (i, j) is T; and a method to calculate the grid geometry characteristics of the targeting grids includes: calculating a pattern density of the surrounding grids (i, j) through d_(ij)=Σ_(t=1) ^(T)d_(t), d_(t)=S_(t)/(D_(i)×D_(j)), where S_(t) is an area size of a i^(th) graphic pattern in the surrounding grids (i, j), D_(i)×D_(j) is an area size of the surrounding grids (i, j), and d_(t) is of a contribution of t^(th) graphic pattern to the pattern density of the surrounding grids (i, j); calculating a linewidth of the graphic patterns of the surrounding grid (i, j) through w_(ij)=Σ_(t=1) ^(T)w_(t)S_(t)/Σ_(t=1) ^(T)S_(t), where w_(t) is a linewidth of the t^(th) graphic pattern in the surrounding grids (i, j), and S_(t) is the area size of the t^(th) graphic pattern in the surrounding grids (i, j); calculating a perimeter of the graphic patterns of the surrounding grid (i, j) through p_(ij)=Σ_(t=1) ^(T)p_(t), where p_(t) is a total length of all edges of the tth graphic pattern inside the surrounding grids (i, j), and does not include a length of edges of the tth graphic pattern outside the surrounding grid (i, j) or at the boundary of the surrounding grid (i, j); and calculating a pattern density d_(ij), a linewidth of the graphic patterns w_(ij), and a perimeter of the graphic patterns p_(ij) for each surrounding grid (i, j) of the targeting grids by successively changing i from 1 to N and j from 1 to M to obtain the grid geometry characteristics of the targeting grids.
 8. The CMP simulation method according to claim 7, wherein: the t^(th) graphic pattern in the surrounding grids (i, j) has a rectangular shape; and the method to calculate the linewidth w_(t) of the graphic patterns includes calculating the width of the rectangle.
 9. The CMP simulation method according to claim 7, wherein the t^(th) graphic pattern in the surrounding grids (i, j) has an irregular shape, the method to calculate the linewidth w_(t) of the graphic patterns includes: breaking the t^(th) graphic pattern into a plurality of sub graphic patterns, wherein each sub graphic pattern has a rectangular shape; calculating the linewidth of each sub graphic pattern of the t^(th) graphic pattern; and calculating the linewidth of the t^(th) graphic pattern through w_(t)=Σ_(q=1) ^(Q)w_(tq)S_(tq)/Σ_(q=1) ^(Q)S_(tq), where Q is a number of the sub graphic patterns in the t^(th) graphic pattern, w_(tq) is the linewidth of the qth sub graphic pattern of the t^(th) graphic pattern, and S_(tq) is an area size of the qth sub graphic pattern of the t^(th) graphic pattern.
 10. The CMP simulation method according to claim 7, wherein locating the first hot spots on the chip pattern layout after performing CMP simulation based on the grid geometry characteristics of the targeting grids includes: selecting a CMP simulation model; and performing CMP simulation using the pattern density d_(ij), the linewidth of graphic patterns w_(ij), and the perimeter of graphic patterns p_(ij) of each surrounding grid as parameters to locate the first hot spots on the chip pattern layout.
 11. The CMP simulation method according to claim 1, wherein generating the optimized grid geometry characteristics by modifying the grid geometry characteristics of the targeting grids based on the weighted average grid geometry characteristics and the defined first hot spots includes: replacing the grid geometry characteristics with the weighted average grid geometry characteristics for surrounding grids corresponding to the first hot spots; and keeping the grid geometry characteristics for surrounding grids in the targeting grids not corresponding to the first hot spots.
 12. The CMP simulation method according to claim 1, wherein performing CMP simulation to locate the second hot spots based on the optimized grid geometry characteristics includes: selecting a CMP simulation model; and performing the CMP simulation using the optimized grid geometry characteristics as parameters to locate the second hot spots on the chip pattern layout.
 13. A CMP simulation device, comprising: a chip pattern layout input module, configured to input a chip pattern layout, wherein the chip pattern layout includes a plurality of graphic patterns; a targeting grids data module, configured to partition the chip pattern layout into targeting grids, wherein the targeting grids include a plurality of surrounding grids, and the targeting grids data module also calculates grid geometry characteristics of the targeting grids; a hot spot location module, configured to perform a CMP simulation to locate first hot spots on the chip pattern layout based on the grid geometry characteristics of the targeting grids; a grids shift data module, configured to shift the targeting grids and generate shifted grids, wherein the grids shift data module also calculates weighted average grid geometry characteristics of the targeting grids and the shifted grids; and a grid geometry characteristic optimization module, configured to generate optimized grid geometry characteristics by modifying the grid geometry characteristics of the targeting grids based on the weighted average grid geometry characteristics and the defined first hot spots, wherein: the hot spot location module also performs the CMP simulation to locate second hot spots on the chip pattern layout based on the optimized grid geometry characteristics.
 14. The CMP simulation device according to claim 13, wherein: the chip pattern layout includes a dielectric layer in addition to the plurality of graphic patterns; and the first hot spots and the second hot spots are defined as a portion of the chip pattern layout with top graphic patterns having a height difference relative to a base plane exceeding 200 Å after a corresponding CMP simulation process, wherein: the dielectric layer isolates neighboring graphic patterns; and the base plane is defined as a plane with a height equal to an average height of top surfaces of the graphic patterns and a top surface of the dielectric layer.
 15. The CMP simulation device according to claim 13, wherein: the chip pattern layout includes a dielectric layer in addition to the plurality of graphic patterns; and the first hot spots and the second hot spots are defined as a portion of the chip pattern layout with the top graphic patterns having a thickness exceeding 110% of a standard graphic pattern thickness, wherein: the dielectric layer isolates neighboring graphic patterns; and the standard graphic pattern thickness is a preset thickness determined according to experience.
 16. The CMP simulation device according to claim 13, wherein: the targeting grids data module partitions the chip pattern layout into the targeting grids along a first direction and a second direction, wherein the plurality of surrounding grids of the targeting grids all have an identical shape and an identical size, a dimension of each surrounding grid along the first direction is D_(i), and a dimension of each surrounding grids along the second direction is D_(j); and the grids shift data module shifts the targeting grids a distance of D_(i)/n along the first direction to form first shifted grids, shifts the targeting grids a distance of D_(j)/n along the second direction to form second shifted grids, and shifts the targeting grids a distance of D_(i)/n along the first direction and then a distance of D_(j)/n along the second direction to form third shifted grids, wherein n is a positive integer.
 17. The CMP simulation device according to claim 13, wherein the grid geometry characteristics of the targeting grids includes pattern density, linewidth of graphic patterns, perimeter of graphic patterns of each surrounding grid of the targeting grids.
 18. The CMP simulation device according to claim 13, wherein after the grids shift data module generate shifted grids by shifting the targeting grids, the function of the grids shift data module further includes: calculating grid geometry characteristics of the shifted grids; and calculating the weighted average grid geometry characteristics of the targeting grids and the shifted grids using a weighted average method.
 19. The CMP simulation device according to claim 13, wherein using the grid geometry characteristics optimization module to generate the optimized grid geometry characteristics by modifying the grid geometry characteristics of the targeting grids includes: replacing the grid geometry characteristics with the weighted average grid geometry characteristics for surrounding grids corresponding to the first hot spots; keeping the grid geometry characteristics for surrounding grids in the targeting grids not corresponding to the first hot spots; and the weighted average grid geometry characteristics of the surrounding grids corresponding to the first hot spots together with the grid geometry characteristics of the surrounding grids not corresponding to the first hot spots form the optimized grid geometry characteristics.
 20. The CMP simulation device according to claim 13, further including: a grid geometry characteristic output module to send the optimized grid geometry characteristics generated in the grid geometry characteristic optimization module into the hot spot location module. 